●  Many innovations require tailored ASICs with sophisticated features at high speeds
●  Many inventors are SME's with small budgets
●  Your market may be small @ perhaps 1,000 to 10,000 devices year
●  Full-custom ASIC development takes time & is expensive
●  Prototyping & production is very expensive for small volumes
●  Gate arrays can reduce entrance costs for CMOS circuitry
●  For RF & analog designs, options have been limited
●  advICo has developed a flexible, analog-capable BiCMOS gate array which allows rapid design of small & medium complex designs up to >10GHz clock rates with low mask cost